CapabilitiesSoC AI algorithm R&D

01 · EDGE AI DEVELOPMENT

Vision models that
belong on the edge.

We shape detection, tracking and image-understanding workflows around the silicon, memory, thermal and latency realities of RK, HiSilicon and Novatek platforms.

Embedded SoC and camera module in an AI vision test environment

DEPLOYMENT STACK

The model, ISP and runtime should be designed as one system — not integrated as an afterthought.

01
RKNN · MPP · RGA

Rockchip RK: RKNN conversion, quantization and edge inference deployment

MODEL TOOLCHAIN & MEDIA PATH

02
HiMPP · ISP · NNIE/NPU

HiSilicon: HiMPP media pipeline, ISP and NNIE/NPU inference integration

IMAGE–INFERENCE CO-DESIGN

03
ISP · Codec · NPU

Novatek: smart-camera ISP, codec and NPU workflow adaptation

CAMERA-TO-ALGORITHM ADAPTATION

Where this work matters

Edge AI that survives the product constraints.

Algorithm development is most valuable when it follows the actual scene, camera and deployment target from the start.

01

RK adaptation

Profile the model on RKNN, then align quantization, MPP/RGA image flow and runtime behavior with the target board.

02

HiSilicon adaptation

Connect the HiMPP and ISP path to NNIE or NPU inference so image processing and model input remain consistent.

03

Novatek adaptation

Fit algorithm logic to the smart-camera ISP, encoding and NPU path with the available memory and thermal budget in view.

PROJECT OUTPUTS

What the team receives

A practical handoff connects the selected SoC toolchain, model behavior and camera pipeline to the target board.

Platform adaptation matrix

A concise view of supported operators, model format, memory, heat, latency and media-path constraints by SoC.

Image-to-model baseline

Documented ISP, preprocessing, quantization and inference settings for repeatable tuning on the selected platform.

Deployment package

Runnable artifacts, integration notes and a measured validation plan for the target RK, HiSilicon or Novatek device.

PROJECT PATH

Progress with evidence, not assumptions.

  1. 01

    Frame the target scene

  2. 02

    Profile viable models

  3. 03

    Tune the image pipeline

  4. 04

    Package the release

ENGINEERING QUESTIONS

The conversations that shape the system.

01Can an existing model be moved to an edge SoC?

Yes. We begin with profiling, identify unsupported or expensive operations, then shape the model and runtime around the chosen platform.

02How do you choose between RK, HiSilicon and Novatek?

The decision follows the sensor and ISP path, native model toolchain, codec and host interfaces, plus the thermal, performance and volume constraints — not a one-size-fits-all benchmark.

03Do you only provide algorithm code?

No. The work includes the image pipeline, runtime packaging and engineering notes needed to bring the algorithm into a camera product.

ORIVERX / CAPABILITIES / 01

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